As scaling challenges are discovered in attempts to integrate more and more transistors onto a single substrate, new technologies are developed. Previously, increases in transistor density were largely achieved by the miniaturization of the transistor itself. However, there is a physical limit to the degree of miniaturization that is possible. In an attempt to continue integrating more transistors on a single device, the concept of vertical devices, also known as 3D devices, has gained momentum. That is, while traditional transistors are made with the source, drain and gate region horizontally oriented, vertical gates build these features in the vertical direction, thereby reducing the horizontal footprint of each device.
Accordingly, 3D NAND structure is proving attractive due to its capability to increase the array density by simply stacking more layers within a similar footprint. As more layers are stacked, the pitch between elements increases thereby also decreasing the number of elements horizontally oriented. As such, the scalability of 3D structure is limited.
Accordingly, there is a need in the art to eliminate the need to perform deep slit etching thus reducing limits in the scalability and efficiency of the 3D structure.